1. Field of the Invention
The present invention relates to a semiconductor integrated circuit including two or more master interfaces performing data transfer request and a slave interface receiving the data transfer request, and a method of measuring a maximum delay of the semiconductor integrated circuit.
2. Description of Related Art
FIG. 5 shows a related semiconductor integrated circuit. Two or more master interface (IF) circuits 111a and 111b, and a slave IF circuit 131 are connected through a system bus control circuit 121. The master IF circuits 111a and 111b perform data transfer request for FIFO 151a and FIFO 151b on the slave IF circuit 131, and data transfer request from the FIFO 151a and FIFO 151b to the slave IF circuit 131. The slave IF circuit 131 is a circuit receiving the data transfer request from the master IF circuits 111a and 111b. 
The system bus control circuit 121 includes an arbiter circuit 122 arbitrating use of a bus, a slave IF circuit 131, and a data selecting circuit 123 controlling transmission of data between the FIFOs 151a and 151b. The FIFOs 151a and 151b are controlled by FIFO control circuits 152a and 152b, respectively, for data input and output. Control signals Sa, Sb, and Sc are transmitted among the master IF circuits 111a and 111b, the slave IF circuit 131, and the arbiter circuit 122.
First, the detail of the control signal Sa, the control signal Sb and the control signal Sc will be explained. Unless mentioned otherwise, High means active in logic. The control signal Sa includes REQa, ACKa, RD/WRa, address a, data length a, RDa, and WRa. The control signal Sb includes REQb, ACKb, RD/WRb, address b, data length b, RDb, and WRb. The control signal Sc includes transfer start c, RD/WRc, address c, data length c, RDc, WRc, data input c, and data output c.    REQa, REQb: data transfer request signals from the master IF circuits 111a, 111b to the system bus control circuit ACKa, ACKb: data transfer request accept signals from the system bus control circuit to the master IF circuits 111a, 111b     address a, address b: addresses of transfer data from the master IF circuits 111a, 111b to the slave IF circuit 131 data length a, data length b: lengths of transfer data from the master IF circuits 111a, 111b to the slave IF circuit 131    RD/WRa, RD/WRb: recognition signals of read (High) or write (Low) from the master IF circuits 111a, 111b to the slave IF circuit 131    RDa, RDb: read signals from the system bus control circuit 121 to the master IF circuits 111a, 111b     WRa, WRb: write signals from the system bus control circuit 121 to the master IF circuits 111a, 111b     address c: an address of transfer data from the system bus control circuit 121 to the slave IF circuit 131    data length c: a length of transfer data from the system bus control circuit 121 to the slave IF circuit 131    RD/WRc: a recognition signal of read (High) or write (Low) from the system bus control circuit 121 to the slave IF circuit 131    RDc: a read signal from the slave IF circuit 131 to the system bus control circuit 121    WRc: a write signal from the slave IF circuit 131 to the system bus control circuit 121    transfer start c: a data transfer start request signal from the system bus control circuit 121 to the slave IF circuit 131
Operation of the FIFO 151a and the FIFO control circuit 152a which is the control circuit thereof will now be explained. Data is input to the FIFO 151a as data input INa. The data is the one in which real time is important such as video or audio data and the FIFO 151a and the FIFO control circuit 152a cannot reject the data receiving. After the FIFO 151a has received the data, the FIFO control circuit 152a performs data transfer request to the slave IF circuit 131 by outputting the STARTa signal to the master IF circuit 111a. The FIFO control circuit 152a, in response to the input ENDa signal, recognizes that data transfer which has been requested previously is finished and next data is able to be transferred. Note that, in the initial state, the FIFO control circuit 152a can output the STARTa signal regardless of the ENDa signal. After outputting the STARTa signal, data input continues from the data input INa to the FIFO 151a. Therefore, if the ENDa signal is not input, the input data overflows the limited buffer of the FIFO 151a and data are damaged. In this case, for example, the FIFO control circuit 152a outputs an overflow detection signal to inform an external device of it.
Next, the data transfer from the master IF circuit 111a to the slave IF circuit 131 will be described with reference to a timing chart. FIG. 6 shows a timing chart of each signal in the related semiconductor integrated circuit. When the master IF circuit 111a receives a data transfer request STARTa signal from the FIFO control circuit 152a, the master IF circuit 111a outputs REQa to the system bus control circuit. At this time, in order to show it is a data output processing to the slave IF circuit 131, the master IF circuit 111a sets an RD/WRa signal to “Low”, and outputs necessary values to an address a signal and a data length a signal.
The arbiter circuit 122 in the system bus control circuit 121 outputs a data transfer enable signal ACKa to the master IF circuit 111a while the other master IF circuits do not use the system bus. At the same time, the system bus control circuit 121 outputs address c signal, data length c signal, RD/WRc signal, and a transfer start c signal, which is start request signal of data transfer, to the slave IF circuit 131.
The slave IF circuit 131 outputs WRc signal or RDc signal to the system bus control circuit 121 in accordance with RD/WRc signal. In this timing chart, the master IF circuit 111a transfers the data to the slave IF circuit 131. In this case, WRc signal becomes “High”. The slave IF circuit 131 receives the transfer data by a data output OUTc signal during the WRc signal being “High”. The system bus control circuit 121 outputs WRc signal to the master IF circuit 111a which is valid at that time. That is, in this example, the system bus control circuit 121 sets the WRa signal which is sent to the master IF circuit 111a to “High”.
The master IF circuit 111a outputs the transfer data by a data output a signal in sync with a clock signal during the WRa signal being “High”. The master IF circuit 111a and the slave IF circuit 131 determine that all the data transfers have been finished when the data transfers of data number which are set to the data length a, c have been finished, respectively. As data length a and data length c are the same value, the master IF circuit 111a and the slave IF circuit 131 determine at the same time that the transfers of all data have been finished.
When the master IF circuit 111a has finished the data transfer, the master IF circuit 111a outputs an ENDa signal to the FIFO control circuit 152a which uses the master IF circuit 111a. The slave IF circuit 131 outputs an ENDc signal to circuits which are connected to the slave IF circuit 131. The arbiter circuit 122 in the system bus control circuit 121 also determines that the data transfer of the master IF circuit 111a has been finished by monitoring the control signal Sa and the control signal Sc accompanying the data transfer.
Next, an operation of the FIFO 151b and the FIFO control circuit 152b which is a control circuit of the FIFO 151b will be described. The FIFO 151b outputs data as a data output OUTb. This data is data in which real time is important such as video or audio data, and the FIFO 151b and the FIFO control circuit 152b must keep outputting the data. If the data output is completely stopped or the data output is stopped for more than a period which is acceptable to a data receiving side, a problem such as distortion of a video or an audio will occur. In these cases, the semiconductor integrated circuit informs an external of this problem by outputting underflow detection signal from the FIFO control circuit 152b. If the FIFO 151b is in the state where the FIFO 151b can receive the data, the FIFO control circuit 152b performs the data transfer request to the slave IF circuit 131 by outputting a START b signal to the master IF circuit 111b. The FIFO control circuit 152b recognizes that the data transfer which is previously requested is finished and next data can be transferred by receiving ENDb signal. Note that, in the initial state, the FIFO control circuit 152b can output the STARTb signal regardless of the ENDb signal.
Next, a data transfer from the slave IF circuit 131 to the master IF circuit 111b will be explained. In this example, receiving the data transfer request STARTb signal, the master IF circuit 111b inputs a data transfer request signal REQb to the system bus control circuit 121 one clock later than a REQa signal from the master IF circuit 111a. In this case, the master IF circuit 111b has to wait for a data transfer process termination of the master IF circuit 111a before performing a data transfer request. After the arbiter circuit 122 in the system bus control circuit determines a data transfer of the master IF circuit 111a and the slave IF circuit 131 is terminated (checks the system bus is not used by other masters), the arbiter circuit 122 sets an ACKb signal to High. Following this operation, the data transfer is performed in the same way as the data transfer of the master IF circuit 111a and the slave IF circuit 131 described above. In this case, since the data transfer is from the slave IF circuit 131 to the master IF circuit 111b, an RD/WRb signal is High.
As explained above, the waiting time until when the ACKb signal of the master IF circuit 111b becomes High depends on the data length and the timing of the data transfer processing of the master IF circuit 111a and the slave IF circuit 131.
However, the time for data transfer completion is not constant for various reasons (software processing content, interruption processing of an LSI external input signal, and variations of compression/expansion processing amount of video/audio data) in accessing the slave IF circuit by the master IF circuit. Thus, the operation check in a condition where the system bus is under a peak load is extremely difficult, or it may be impossible to even determine whether the load is the peak load or not.
By the way, a DMA bus load varying device to perform concurrence test of a DMA device, peak load test, and appreciation of system performance without connecting a plurality of DMA devices to a DMA bus is disclosed in Japanese Unexamined Patent Application Publication No. 58-151631 (patent document 1). In the technique disclosed in patent document 1, a request of the DMA bus can be executed by an optional transfer period, an optional transfer area, and an optional mode (memory mode/write). Further, a timer to measure j period until the completion of the block transfer having any desired size is optionally provided to have a function as a DMA bus load varying device and a DMA bus simulator.